In computer systems, parallel buses such as the PCI (Personal Computer Interconnect) bus have been used to achieve high bandwidth connectivity between peripheral devices and processors and between multiple processors. In high speed data communications, serial interconnection schemes such as the Fibre Channel have been developed to produce high bandwidth within a single serial connection. These serial interconnection schemes have been used in computer systems, but have carried a cost of a unique interface requirement and a protocol that is incompatible with other peripheral devices. In addition, when they are tightly integrated into a computer system, the system controller circuits must be modified to use this connection, requiring custom components to be developed which raise the overall cost and complexity of the computer system.
The Fibre Channel has an overhead connected with link protocol and link recovery that is prohibitive when bandwidths are required which push the limit of the channel. The initialization times for a device can be on the order of milliseconds. This is a delay which is unnecessary when operating within a system where all devices are known or device information does not have to be polled every time a link failure occurs.
Within the realm of the parallel bus computer, interconnection is also a problem. Parallel bus interconnects require a high trace density on a circuit board, usually requiring a multitude of circuit board layers for both trace implementation and EMI (electromagnetic interference) and RFI (radio frequency interference) shielding. Serially connected buses reduce this requirement substantially but have produced an added cost of incompatibility with parallel connected components and have lower bandwidth than parallel connected buses.
Therefore a need existed to provide devices and methods for reducing interconnect signal line count by using a serially connected bus and to improve the operation of the existing serial buses such as the Fibre Channel so that the bandwidth can be improved to make this serial connection function as a practical alternative to existing parallel buses. A need also existed to provide connectivity to present buses such as the PCI bus, to maintain compatibility with present controllers and peripherals.